The present invention relates to a semiconductor integrated circuit, and more particularly to a duty cycle correction circuit of a semiconductor integrated circuit.
In a system including a variety of semiconductor devices having various functions, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells corresponding to addresses inputted together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to input/output data at higher speed. As semiconductor integrated circuit (IC) technologies are rapidly developed, the operating speed of the data processor increases, but the data input/output speed of the semiconductor memory device does not keep up with the increasing operating speed of the data processor.
Many attempts have been made to develop semiconductor memory devices that can increase data input/output speed up to the level required by the data processor. One of these semiconductor memory devices is a synchronous memory device that receives a system clock and processes data in synchronization with the system clock. Specifically, the synchronous memory device outputs or receives data to or from the data processor at each period of the system clock. However, even the synchronous memory device could not keep up with the operating speed of the data processor, and thus a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or receives data at each transition of the system clock. That is, the DDR synchronous memory device outputs or receives data in synchronization with falling edges and rising edges of the system clock.
A duty cycle ratio of the system clock inputted to the DDR synchronous memory device must be maintained at 50% in order to output data at rising and falling edges of the system clock. If the duty cycle ratio of the system clock is not 50%, a processing margin in the operation of outputting data at the rising edge of the system clock becomes different from that in the operation of outputting data at the falling edge of the system clock. As the frequency of the system clock is increasing, the deficient operation processing margin at one of the rising and falling edges means that it is difficult to process data stably.
Therefore, the DDR synchronous memory device includes a duty cycle correction circuit for correcting the duty cycle ratio of the system clock to 50%. Further, the DDR synchronous memory device includes a delay locked loop (DLL) for compensating a delay time of the system clock until data is outputted after the system clock is received. The DLL outputs a delay locked clock, called a DLL clock. If the semiconductor memory device outputs data in synchronization with the delay locked clock, the data are outputted in synchronization with the rising and falling edges of the system clock. The duty cycle correction circuit of the DDR synchronous memory device compensates the duty cycle ratio of the DLL clock outputted from the DLL.
When the semiconductor memory device uses the system clock internally, it can use a received clock a duty cycle ratio of which is corrected by the duty cycle correction circuit. The duty cycle correction circuit can be used to correct the duty cycle ratio of the clock in various kinds of semiconductor devices.
A typical duty cycle correction circuit corrects a duty cycle ratio of a clock using a clock and an inverted clock. When the frequency of the system clock is very high, the duty cycle ratio of the system clock is adjusted. Since a delay time occurring in the operation of inverting the clock having the adjusted duty cycle ratio is not relatively small, the duty cycle correction circuit corrects both the clock and the inverted clock.
During this process, however, the phase difference between the clock and the inverted clock may not become 180°, that is, their phases are distorted. In this case, if the semiconductor memory device operates using the clocks outputted from the duty cycle correction circuit, it cannot perform the predefined operations at each transition of the system clock. If the phase difference between the duty cycle-corrected system clock and the inverted clock is not 180°, data may be outputted irregularly even though the semiconductor memory device outputs the data at each transition of the duty-corrected system clock.